The present teachings relate generally to interconnection systems, and, more particularly, to alignment tolerant dense optical interconnect systems which incorporate the use of rod lenses or infinite conjugate imagers. The present invention includes array geometries for devices such as emitters and detectors that provide for compactness, crosstalk, wiring, and other advantages when used in a parallel optical interconnect system such as the optical data pipe devices described herein.
With the advent of substantial new performance levels in high bandwidth digital and analog electro-optic systems, there exists a greater need to provide dense, alignment tolerant interconnection capability. This is especially true in digital computing systems; in analog systems such as phased array radar; and in high bandwidth optical carriers in communication systems. However, it should be realized that these are just several of numerous systems which benefit from application of high-bandwidth electro-optic interconnection.
In many current and future systems light beams are modulated in a digital and/or analog fashion and used as “optical carriers” of information. There are many reasons why light beams or optical carriers are preferred in these applications. For example, as the data rate required of such channels increases, the high optical frequencies provide a tremendous improvement in available bandwidth over conventional electrical channels such as formed by wires and coaxial cables. In addition, the energy required to drive and carry high bandwidth signals can be reduced at optical frequencies. Further, optical channels, even those propagating in free space (without waveguides such as optical fibers) can be packed closely and even intersect in space with greatly reduced crosstalk between channels.
Conventional electrical interconnection over wires or traces is reaching severe performance limits due to density, power, crosstalk, time delay, and complexity. For example, chip scaling continues to provide for a doubling of transistors on a chip every 18 months. A 2 cm×2 cm chip currently requires 2 km of wires or traces for interconnection with 6 layers of metal and the complexity exponentiates with the number of metal layers. With designs using 0.18 micron wires, 60% of the delay is from the interconnects themselves. In shrinking from 0.5 micron wires to 0.18 micron wires on chip, the RC time constant increases by a factor of 10. Using optical interconnection, the power dissipation does not scale with the length of interconnection, and optical interconnects are superior for short signal rise times. Similar advantages of optical interconnection over electrical interconnection pertain to longer range interconnection, e.g., from chip-to-chip, intra-board, inter-board, and computer-to-peripheral.
Other optical interconnect approaches suffer from critical alignment tolerances; restrictive focusing, component separation and vibration tolerance requirements; insertion loss which limits speed and power efficiency; bulky and large-footprint optical systems; limited density and scalability; lack of physical flexibility and compliance of the interconnect, and the need to provide an excessively protective environment in order to maintain optical alignment over time.